A process of designing an integrated circuit (IC) comprises multiple steps. Building blocks of the IC under design are typically represented by parameterized cells (Pcells). During a schematic (netlist) stage, the Pcell is a symbolic representation of an electronic entity. During a layout stage, a user application generates a request to evaluate the Pcell by passing parameter values and identity of the Pcell desired. The request results in generation of an instantiation of a physical, fixed structure of the Pcell. This structure is referred to as design data and is compatible with an electronic design automation (EDA) vendor's database.
With the continuing trend towards miniaturization of integrated circuits (ICs), there is a need for transistors to have higher drive currents with increasingly smaller dimensions. Fin field effect transistor (finFET) technology is becoming more prevalent as device size continues to shrink and, in some cases, is used to implement designs previously implemented with planar technology. There are many existing designs implemented in planar technology, and new designs are continuing to be developed. Adapting planar designs to finFET technology is more than simply accounting for a different critical dimension. As finFET technology represents a new paradigm compared to planar technology, there are numerous issues that can complicate the migration from planar technology to finFET technology.